orderto preventCMOS latch - up

the previous techniquesto preventCMOS latch - up

when the different voltage supplies connected to the circuit do not reach their full voltage levels at the same timethereby preventinglatch - up in the CMOS circuit

A method for sizing one or more current - limiting devicesto preventlatch up within a CMOS circuit

4 ) External Links : USPTO , USPTO Assignment , EspacenetMethod and apparatusto preventlatch - up in CMOS devicesUS 6359316

Since the p+-type diffusion 9 helpspreventCMOS latch - up

Patent US6359316 - Method and apparatusto preventlatch - up in CMOS devices

Cypress Semiconductor Corp. Method and apparatusto preventlatch - up in CMOS devices

Sep 19 , 1997Mar 19 , 2002Cypress Semiconductor Corp . Method and apparatusto preventlatch - up in CMOS devicesUS6432759

increasing the die size of the device....http://www.google.com/patents/US6359316?utm_source=gb-gplus-sharePatent US6359316 - Method and apparatusto preventlatch - up in CMOS devicesAdvanced

1 , 3 and 4 of the drawings were designed in the N - well technology with all wells connected to the terminal VDD except for those wells associated with P - channel transistors P1 , P1 ' , P12 , and P12 ' and with appropriate guard rings provided for the transistors forming the serial arrangements in the control or enabling circuit 10 and in the disabling or releasing circuit 10to preventlatch - up in the CMOS circuits

with the CMOS latch cell disconnected from the power supplyis seton the CMOS latch

Voltage ramping ... simultaneousto preventCMOS latch - up

a logic HIGH or logic LOW signalwill triggerthe CMOS latch

A voltage dropcan causelatch - up on any CMOS device

14too can triggerlatch - up of the CMOS

The current - limiting device is configuredto preventlatch up of the CMOS circuit

You need a diode in parallel with the charging resistor to dump the charge in the capacitor when you power down the rails , a voltage on an input when the supply goes downcan causeCMOS to latch up

the comparatorsetsa CMOS latch

Various CMOS designs have been conceivedto preventCMOS latch - up

It only takesto causea CMOS latch - up

the fully recessed , field oxidepreventslatch - up in the CMOS circuits

A lightning strikemay triggera CMOS latch - up

a parasitic lateral bipolar transistor(passive) caused byCMOS latch - up

other manners in whichto preventlatch up in CMOS circuits

leakage current flow between the two MOSFETS of the CMOS devicecan causelatch - up of the CMOS device

the use of a retrograde well structure(passive) can be prevented byLatch - up in a CMOS device

either positive or negative voltage spike on a I / O pin causing a component to either latch - up or rather short a pint to either Vcc or groung(passive) caused byCMOS part latch - up

A channel - stop doping may also improve well conductivitythus preventinga CMOS latch - up from happening

placing the guard ring into chip layoutto preventlatch - up in CMOS

an effortto preventCMOS latch - up

Careful design methodspreventCMOS latch up

because the well ( n - well ) remains at a floating 0 V just until the application of the supply voltagethus causinglatch - up of the CMOS

The structure of the present inventioncan preventlatch - up of CMOS

describeto preventlatch up in CMOS

a negative resistance statecan leadto CMOS latch - up

Substrate currents occurring during operationcan triggerlatch - up in CMOS circuits

the pnp parasitic bipolar transistor(passive) is caused bylatch - up in the CMOS device

a variety of mechanisms , including but not limited to terminal overvoltage stress , transient displacement currents , and ionizing radiation , such as neutron or alpha radiation(passive) can be caused byLatch up within a CMOS circuit

parasitic bipolar transistors from the source / drain elements of the CMOS and other device elements such as the N and P wells and the substrate region(passive) is typically caused byCMOS latch - up