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cache performance ... e.g. , speculatively executed blockscan causeadditional cache misses
the table(passive) caused byadditional cache misses
This strategywill causeadditional cache misses
by the fact that a data object to be used is not present in the cache memory at program execution time(passive) caused bycache miss
even when executing the same build commandcausingcache misses full
your codewill causeextra cache misses
assuming the length fits into a register or at leastcauseadditional cache misses
the same code in 32bitcausesextra cache misses
by the fact that data objects can not be loaded into the cache memory at one time(passive) caused bycache miss
these updatescausecache hit misses
can push out needed datacausingsubsequent cache misses
by different memory location(passive) caused bycache miss
one cycle except memory instructionscausecache miss
by client requests(passive) caused bycache miss
Instruction fetchcausescache miss
> > threads keep migrating between CPUscausingfrequent cache misses
because the threads keep migrating between CPUscausingfrequent cache misses
This situationcausescache miss
a pattern of memory accessescausesrepeated cache misses
an erasure(passive) caused bysubsequent cache misses
the spotcausingcache miss
memory accessescausesrepeated cache misses
fine - grained system - call scheduling with WSCcausedfrequent cache misses
context - switchingwould causecache miss
inspectingcausecache miss
that are all over the place in memorycausingtons of cache misses
When n is too large and the cache size of the machine is too small , the accessed array elements in one loop iteration ( for example , i = 1 , j = 1 to n ) may cross cache linescausingcache misses
by program line(passive) caused byCache misses ( reads
by the first access to a block that has never been in the cache Capacity misses(passive) caused bycache misses
by the first access to a block that has never been in the cache Capacity misses These(passive) caused bycache misses
by the first access to a block that has never been in the cache Capacity misses ( cold - start(passive) caused bycache misses
visiting every data mapped to the first cache set(passive) are caused byThe cache misses
by the first access to a block that has never been in the cache Capacity(passive) caused bycache misses
inefficient / missing indexes , pessimistic concurrency causing unnecessary blocking operations , a hyper - threading incompatibilitycausedcache misses , etc
If many memory accessesleadto cache misses
by the first access to a block that has never been in the cache(passive) caused bycache misses
by the first access to a memory location(passive) are caused byCache misses
data requestsresultin cache misses
were you sayingwas ... causingcache missed
memory accesses ... thoseresultin cache misses
to much active evidence datacausedto much active evidence data
in higher CPU and disk IO usageresultsin higher CPU and disk IO usage
the page requests to consume unnecessary system resourcescausesthe page requests to consume unnecessary system resources
the page requests to consume unneccesary system resourcescausesthe page requests to consume unneccesary system resources
conflicts even when overall cache usage is not heavyto setconflicts even when overall cache usage is not heavy
cache misscausecache miss
really unpredictable resultswould causereally unpredictable results
an update to the fast hardware cache or the fast cache in main memorymight causean update to the fast hardware cache or the fast cache in main memory
the cache controller to address remote memory via SCI to get the datacausesthe cache controller to address remote memory via SCI to get the data
an update to de fast hardware cache or de fast cache in main memorymight causean update to de fast hardware cache or de fast cache in main memory
from the first cache accessresultedfrom the first cache access
delays in execution of the instruction since the cache is typically first filled with the instructioncausesdelays in execution of the instruction since the cache is typically first filled with the instruction
in a performance hitresultsin a performance hit
in a cache loadresultsin a cache load
to lotsleadingto lots
a read to this pagecausesa read to this page
other problemsmay causeother problems
in a write backcould resultin a write back
a fetch to system memorycausesa fetch to system memory
in a slow database callresultedin a slow database call
in cache but invalidresultin cache but invalid
much more overall latencycan causemuch more overall latency
a replacement line to be selected from one of the ways of the cache memory 40 already allocated to thread B if the particular rowcausesa replacement line to be selected from one of the ways of the cache memory 40 already allocated to thread B if the particular row
the cache management unit 62 to send the line address of the requested instruction to a group of storage management functions 64will causethe cache management unit 62 to send the line address of the requested instruction to a group of storage management functions 64
the cache management unit 62will causethe cache management unit 62
a linefill process to take place as a result of which a line of data is retrieved into the data cache 90will ... causea linefill process to take place as a result of which a line of data is retrieved into the data cache 90
the instruction cache to be flushedcausingthe instruction cache to be flushed
a readcausesa read
in a request for 1 module instead of the entire bottom load queueresultsin a request for 1 module instead of the entire bottom load queue
delays(passive) caused bydelays
event(passive) caused byevent
A similar delay(passive) can be caused byA similar delay
the slow downis causingthe slow down
us to fetch things from the RAM , or even worse , from the page filewill causeus to fetch things from the RAM , or even worse , from the page file
huge performance overhead if occurs oftenmight causehuge performance overhead if occurs often
a whole line to be loadedcausesa whole line to be loaded
a loadcausesa load
the pipeline to wait until the cache is refilled with the missing contentcausesthe pipeline to wait until the cache is refilled with the missing content
from an attempt to retrieve a second data itemresultingfrom an attempt to retrieve a second data item
to the transfer of a blockleadingto the transfer of a block