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which instruction or instructionsare causingthe cache misses
load1 ... the instructioncausesL1D - cache misses
an example of a program including an instruction that is likelyto causecache misses
a few requests ( the onestriggercache misses
data or instructions ... i.e. , addressescausedcache misses before
1st access to a block(passive) created bythe Cache misses
load instructions that are likelyto causecache misses
program instructions that are likelyto causecache misses
at least one instruction(passive) caused bycache misses
a particular region of instruction addresses as follows(passive) caused bycache misses
the code that pushes & gt(passive) caused bythe cache misses
70 % of the requestsresultedin cache misses
load requests(passive) caused bycache misses
your scheduler codeto causecache misses
code designedto triggercache misses
Inlining codecould contributeto cache misses
java code(passive) caused bythe cache misses
a pattern of memory accessescausesrepeated cache misses
the number of instruction address changesleadto cache misses
sequential addressescausecache misses
the addresses of dataresultedin cache misses
Normally simultaneous requests for the same objectresultin cache misses
Branch instructionsoften resultin cache misses
instructions for those itemsmay causecache misses
store instructions(passive) triggered bycache misses
Unrolled code , being larger , is more likely to exceed the size of the instruction cacheleadingto cache misses
two requests ... the same addressresultedin cache misses
cache - coherence requestsresultingfrom cache misses
any future access requestsresultingfrom cache misses
a plurality of operand memory addresses referenced by operand memory requestsresultedin cache misses
a plurality of memory addressescausedcache misses before
column ... more likelyto causecache misses
a prefetch ... likelyto resultin cache misses
A compiler ... likelyto resultin cache misses
having an overly huge code image(passive) caused bycache misses
a load instruction by said processor to load a value from said inaccessible source virtual address(passive) triggered bycache miss
an application ’s most significant memory access patternscausingcache misses
a significant number of memory accessescausecache misses
preload instructions in the instruction sequence of the application program object code ... the offending instructionscreatelong cache misses
pointers ... non - contiguous memory addressescausecache misses
data access latency(passive) caused bydata access latency
unpredictable memory latency(passive) caused byunpredictable memory latency
latency and timing variations(passive) caused bylatency and timing variations
any time delays(passive) caused byany time delays
delays ( stallsare ... causingdelays ( stalls
architecture minimizes delays(passive) caused byarchitecture minimizes delays
the stall time(passive) caused bythe stall time
increase in latency ( extra proxy processingcan causeincrease in latency ( extra proxy processing
a delaycan ... causea delay
huge performance overhead if it occurs oftenmight causehuge performance overhead if it occurs often
deadlockscan createdeadlocks
from the early eviction of data that may be reused by the clients within the systemresultingfrom the early eviction of data that may be reused by the clients within the system
delays as the program or applicationcan causedelays as the program or application
memory - related delays(passive) caused bymemory - related delays
main memory accesses(passive) caused bymain memory accesses
in a main memory accessresultingin a main memory access
reads from main memorycausingreads from main memory
the number of data fetches(passive) caused bythe number of data fetches
the processor to stall , wasting timecausethe processor to stall , wasting time
to the first thread switching andleadsto the first thread switching and
In uniprocessors : bus traffic and memory - access time(passive) heavily influenced byIn uniprocessors : bus traffic and memory - access time
in a wait while the data is fetched from main memory , by making the cache larger the probability of a cache miss is reduced , but the impact of a miss is still the sameresultin a wait while the data is fetched from main memory , by making the cache larger the probability of a cache miss is reduced , but the impact of a miss is still the same
in older data being retrieved from tape and stored again in the DASD cachemay resultin older data being retrieved from tape and stored again in the DASD cache
disk readcausingdisk read
random diskcausingrandom disk
a stall rightwill createa stall right
the CPU stall(passive) caused bythe CPU stall
the additional time(passive) is caused bythe additional time
the processor to idlecausingthe processor to idle
instruction memory access requests(passive) triggered byinstruction memory access requests
additional disk traffic(passive) is createdadditional disk traffic
new stall conditions(passive) caused bynew stall conditions
a first thread to stallcausea first thread to stall
memory system 270(passive) caused bymemory system 270
part of waiting time(passive) caused bypart of waiting time
nodeList every timeto createnodeList every time
buffered media time(passive) caused bybuffered media time
otherwise wasted time(passive) caused byotherwise wasted time
the memory references to get out of order if the processor were allowed to continue working on later instructions while an earlier instruction that missed the cache was accessing memorycould causethe memory references to get out of order if the processor were allowed to continue working on later instructions while an earlier instruction that missed the cache was accessing memory
pipeline stalls in the DSP ’s cores ... and to prevent write - allocate loads , which would significantly reduce performancecausepipeline stalls in the DSP ’s cores ... and to prevent write - allocate loads , which would significantly reduce performance