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On the other handcausesan extra cache miss
by the fact that a data object to be used is not present in the cache memory at program execution time(passive) caused bycache miss
the control logic ... the second cache - line addressresultedin a cache miss
an instruction cache with a first instruction addresscausesa cache miss
The function being called may not be loaded into the processor 's cachecausinga cache miss
a cache miss and the next addresscauseda cache miss
by the first access to a block that has never been in the cache(passive) caused bya cache miss
a data block associated with another addresscauseda cache miss
information about which instruction tends ... or which command tends to cause a branch prediction miss , for exampleto causea cache miss
An attempt to read such an address from the cachemay resultin a cache miss
a current cache miss address ( i.e. , an addresscausesa cache miss
that data is still not in the cachecausinga cache miss
a cache miss ... the addresscausesthe cache miss
the block ... a cache hithas causedthe cache miss
the next cache line ... the cache linecauseda cache miss
the next cache line after the cache linecauseda cache miss
a load instruction within the I - linehas causeda D - cache miss
the data at the memory addresscausedthe cache miss
by the fact that data objects can not be loaded into the cache memory at one time(passive) caused bycache miss
a cache line in I statewill causea cache miss
the cache lines are received out - of - ordercausesa cache miss
the IP of the load instruction ... , and the latency of the cache misscausingthe cache miss
a line of data ... the processor corecausesa cache miss
a memory read instructioncausesa cache miss
a miss address of the memory locationcausingthe cache miss
any data request from the processor corecausesa cache miss
every cache accessresultsin a cache miss
a load / store instruction within the instruction fetch blockcauseda cache miss
by the first access to a clock that has never been in the cache(passive) caused byA cache miss
cache memoryhas resultedin a cache miss
the cache linecausedthe cache miss
no - cache ' requestcausesa cache miss
the load instruction ... likelyto causea cache miss
data ... the instructioncausedthe cache miss
response to the instruction being executed at timecausinga cache miss
if you put more RAM than what the CPU can cache , any reading from such memory out of that rangewill causea cache miss
the cache accessdoes ... resultin a cache miss
time ... likelyto causea cache miss
data ... likelyto resultin a cache miss
a miss base address of the memory locationcausingthe cache miss
in data being fetched from the magnetic disk layerwill resultin data being fetched from the magnetic disk layer
in higher CPU and disk IO usageresultsin higher CPU and disk IO usage
in a thundering herd of database ( or whateveroften resultingin a thundering herd of database ( or whatever
conflicts even when overall cache usage is not heavyto setconflicts even when overall cache usage is not heavy
performance degrade(passive) is caused byperformance degrade
an update to the fast hardware cache or the fast cache in main memorymight causean update to the fast hardware cache or the fast cache in main memory
the processor to request the needed data from the slower main memorywill causethe processor to request the needed data from the slower main memory
the cache controller to address remote memory via SCI to get the datacausesthe cache controller to address remote memory via SCI to get the data
from the second cache line accessresultingfrom the second cache line access
an update to de fast hardware cache or de fast cache in main memorymight causean update to de fast hardware cache or de fast cache in main memory
from the first cache accessresultedfrom the first cache access
in a performance hit for the servershould only resultin a performance hit for the server
delays in execution of the instruction since the cache is typically first filled with the instructioncausesdelays in execution of the instruction since the cache is typically first filled with the instruction
in a line of data being transferred to the cachewill resultin a line of data being transferred to the cache
in a performance hitresultsin a performance hit
in a cache loadresultsin a cache load
in a request for 1 module instead of the entire bottom loadresultsin a request for 1 module instead of the entire bottom load
in wasted execution timemay ... resultin wasted execution time
a read to this pagecausesa read to this page
other problemsmay causeother problems
in a write backcould resultin a write back
a fetch to system memorycausesa fetch to system memory
in a slow database callresultedin a slow database call
in cache but invalidresultin cache but invalid
much more overall latencycan causemuch more overall latency
a replacement line to be selected from one of the ways of the cache memory 40 already allocated to thread B if the particular rowcausesa replacement line to be selected from one of the ways of the cache memory 40 already allocated to thread B if the particular row
the cache management unit 62 to send the line address of the requested instruction to a group of storage management functions 64will causethe cache management unit 62 to send the line address of the requested instruction to a group of storage management functions 64
the cache management unit 62will causethe cache management unit 62
when even the overhead(passive) caused bywhen even the overhead
on a change to any header filewould resulton a change to any header file
alsocausesalso
a linefill process to take place as a result of which a line of data is retrieved into the data cache 90will ... causea linefill process to take place as a result of which a line of data is retrieved into the data cache 90
the instruction cache to be flushedcausingthe instruction cache to be flushed
a readcausesa read
in a request for 1 module instead of the entire bottom load queueresultsin a request for 1 module instead of the entire bottom load queue
this number to be reducedcausethis number to be reduced
from a cache portion corresponding to instruction codeoriginatedfrom a cache portion corresponding to instruction code
from a READ channel command or a WRITE channel commandresultedfrom a READ channel command or a WRITE channel command
a delay(passive) caused bya delay
delays(passive) caused bydelays